1. Field of the Invention
The present invention relates to automatic arrangement and routing technology for semiconductor integrated circuits and in particular to wiring-capacitance improvement aid devices capable of aiding in improving a point having an error attributable to wiring capacitance only through layout modification, methods of aiding in improvement of wiring capacitance, and media having recorded therein a program aiding in improvement of wiring capacitance.
2. Description of the Background Art
In recent years, there is an increasing demand for more efficient, automatic arrangement and routing tools as semiconductor integrated circuits are increasingly of multi-function, high integration and larger in their operating frequencies.
FIG. 1 is a block diagram for illustrating various files used by a conventional, automatic arrangement and routing tool. Files used by automatic arrangement and routing tool 107 include a net list information file 101 storing net list information produced from a logic circuit designed by a user, a macro cell library 102 used in converting a macro cell (referred to as a "cell" hereinafter) in transistor level, a command file 103 storing a command executed by the automatic arrangement and routing tool, a P&R (automatic arrangement and routing) control file 104 for storing a description, such as a wiring-capacitance constraint on a net and a cell-arrangement constraint, a user definition file 105 for storing e.g. a constraint value of a net on which a wiring-capacitance constraint is imposed, and a layout data file 106 for storing layout data after the automatic arrangement and routing tool performs arrangement and routing.
The net list information produced from the logic circuit designed by the user and is stored previously in net list information file 101 prior to automatic arrangement and routing. Macro cell library 102 stores transistor-level information converted from a cell in arranging and routing the cell. Command file 103 stores in batch-file form a command to be executed when automatic arrangement and routing tool 107 performs arrangement and routing.
In arrangement and routing, the user can constrain the wiring capacitance of a net and cell arrangement and store a description of a wiring-capacitance constraint imposed on the net and a cell-arrangement constraint in P&R control file 104. The user can also store in user definition file 105 such information as a constraint value of a net on which a wiring-capacitance constraint is imposed, a location at which a cell with an arrangement constraint is arranged, and the like.
Automatic arrangement and routing tool 107 successively reads and executes commands in command file 103 to perform arrangement and routing. If any wiring-capacitance constraint on a net and any cell-arrangement constraint are described in P&R control file 104, automatic arrangement and routing tool 107 refers to user definition file 105 and thus performs arrangement and routing to satisfy the constraints. Automatic arrangement and routing tool 107 then stores in layout data file 106 the layout data obtained after the arrangement and routing.
While arrangement and routing is performed in accordance with the procedure described above, the resultant layout data can include inconveniences such as errors attributable to capacitance that are associated with generation an error attributable to connectable, maximum capacitance (referred to as a "Comax error" hereinafter), i.e. a sum of the actual capacitance values of driven cells that exceeds a connectable, maximum capacitance value of a driving cell (referred to as a "Comax value" hereinafter), generation of a timing error when layout data is used to perform timing simulation, and the like.
A procedure of detecting the Comax error is as follows: initially, a tool other than automatic arrangement and routing tool 107 extracts a wiring capacitance, a wiring resistance and the like from the layout data stored in layout data file 106 and stores them in a capacitance and resistance extraction file. Furthermore, still another tool calculates a capacitance value of each cell from the wiring capacitance and the like stored in the capacitance and resistance extraction file for comparison to a Comax value previously stored in a delay library to detect a Comax error.
Conventionally, when an error attributable to capacitance as described above is caused the error is eliminated mainly by enhancing the driving capability of a cell and the arrangement of the cell is hardly modified to eliminate the error. If the arrangement of the cell is modified to eliminate the error, the following operation is required. Elimination of a Comax error, which can be performed relatively readily, will now be described with reference to the layout data shown in FIG. 2.
Initially, the user examines cells connected to a net N1 with a Comax error caused while referring to a net list. As a result, cells C1.1 to C1.4 are extracted. The user also examines any nets connected to cells C1.1 to C1.4 and any cells connected to the nets to extract nets N2.1 to N2.6 and cells C2.1 to C2.5. The user refers to the capacitance and resistance extraction file to obtain the respective current capacitance values of nets N2.1 to N2.6. The user then refers to the delay library to obtain the respective Comax values of cells C1.1 to C1.4 and C2.1 to C2.5 to obtain the respective margins of the capacitance values with respect to the Comax values. Then any cells of the extracted cells that have margin in capacitance are extracted and determined as the cells which can be modified in arrangement.
The user then manually modifies in arrangement the cells which can be modified in arrangement or imposes a capacitance constraint or the like on the cells to perform an engineering change order (ECO) to again perform automatic arrangement and routing.
The method of eliminating errors through modification of cell arrangement described above, however, disadvantageously requires great effort of the layout designer when he or she determines a cell which can be modified in arrangement, since the layout designer normally does not have the drawing of the logic circuit of interest and are accordingly forced to use a net list and layout data after arrangement and routing to determine a cell which can be modified in arrangement. In particular, a net with large fan-out has a large number of cells connected thereto and the net itself is so complex that the layout designer is forced to perform extremely cumbersome operation. In eliminating a timing error, the cause of the timing error must be determined before cell arrangement is modified. This renders the operation further cumbersome.
Moreover, with semiconductor integrated circuits having larger operating frequencies in recent years, an operating margin for delay of each logic circuit can hardly be ensured so that operation can often be ensured only in circuit configuration constructed according to virtual design. This is because when a cell with a capacitance-attributable error is changed in circuit to a cell with a higher driving capacity to eliminate the error, the fixed delay value of the cell itself is increased and an additional, timing error is disadvantageously caused. While there is an increasing need for eliminating errors through modification in cell arrangement, the method described above is not effective as long as the above disadvantageous are not solved.